54 #define _TWR_UART_SETTING_DATA_BITS_7 0x07 << 4
55 #define _TWR_UART_SETTING_DATA_BITS_8 0x08 << 4
57 #define _TWR_UART_SETTING_PARITY_NONE 0x00 << 2
58 #define _TWR_UART_SETTING_PARITY_EVEN 0x02 << 2
59 #define _TWR_UART_SETTING_PARITY_ODD 0x03 << 2
61 #define _TWR_UART_SETTING_STOP_BIT_1 0x00
62 #define _TWR_UART_SETTING_STOP_BIT_2 0x02
63 #define _TWR_UART_SETTING_STOP_BIT_15 0x03
70 TWR_UART_SETTING_8N1 = _TWR_UART_SETTING_DATA_BITS_8 | _TWR_UART_SETTING_PARITY_NONE | _TWR_UART_SETTING_STOP_BIT_1,
73 TWR_UART_SETTING_8E1 = _TWR_UART_SETTING_DATA_BITS_8 | _TWR_UART_SETTING_PARITY_EVEN | _TWR_UART_SETTING_STOP_BIT_1,
76 TWR_UART_SETTING_8O1 = _TWR_UART_SETTING_DATA_BITS_8 | _TWR_UART_SETTING_PARITY_ODD | _TWR_UART_SETTING_STOP_BIT_1,
79 TWR_UART_SETTING_8N2 = _TWR_UART_SETTING_DATA_BITS_8 | _TWR_UART_SETTING_PARITY_NONE | _TWR_UART_SETTING_STOP_BIT_2,
82 TWR_UART_SETTING_8E2 = _TWR_UART_SETTING_DATA_BITS_8 | _TWR_UART_SETTING_PARITY_EVEN | _TWR_UART_SETTING_STOP_BIT_2,
85 TWR_UART_SETTING_8O2 = _TWR_UART_SETTING_DATA_BITS_8 | _TWR_UART_SETTING_PARITY_NONE | _TWR_UART_SETTING_STOP_BIT_2,
88 TWR_UART_SETTING_8N1_5 = _TWR_UART_SETTING_DATA_BITS_8 | _TWR_UART_SETTING_PARITY_NONE | _TWR_UART_SETTING_STOP_BIT_15,
91 TWR_UART_SETTING_8E1_5 = _TWR_UART_SETTING_DATA_BITS_8 | _TWR_UART_SETTING_PARITY_EVEN | _TWR_UART_SETTING_STOP_BIT_15,
94 TWR_UART_SETTING_8O1_5 = _TWR_UART_SETTING_DATA_BITS_8 | _TWR_UART_SETTING_PARITY_NONE | _TWR_UART_SETTING_STOP_BIT_15,
97 TWR_UART_SETTING_7N1 = _TWR_UART_SETTING_DATA_BITS_7 | _TWR_UART_SETTING_PARITY_NONE | _TWR_UART_SETTING_STOP_BIT_1,
100 TWR_UART_SETTING_7E1 = _TWR_UART_SETTING_DATA_BITS_7 | _TWR_UART_SETTING_PARITY_EVEN | _TWR_UART_SETTING_STOP_BIT_1,
103 TWR_UART_SETTING_7O1 = _TWR_UART_SETTING_DATA_BITS_7 | _TWR_UART_SETTING_PARITY_ODD | _TWR_UART_SETTING_STOP_BIT_1,
106 TWR_UART_SETTING_7N2 = _TWR_UART_SETTING_DATA_BITS_7 | _TWR_UART_SETTING_PARITY_NONE | _TWR_UART_SETTING_STOP_BIT_2,
109 TWR_UART_SETTING_7E2 = _TWR_UART_SETTING_DATA_BITS_7 | _TWR_UART_SETTING_PARITY_EVEN | _TWR_UART_SETTING_STOP_BIT_2,
112 TWR_UART_SETTING_7O2 = _TWR_UART_SETTING_DATA_BITS_7 | _TWR_UART_SETTING_PARITY_NONE | _TWR_UART_SETTING_STOP_BIT_2,
121 TWR_UART_SETTING_7O1_5 = _TWR_UART_SETTING_DATA_BITS_7 | _TWR_UART_SETTING_PARITY_NONE | _TWR_UART_SETTING_STOP_BIT_15
uint64_t twr_tick_t
Timestamp data type.
twr_uart_channel_t
UART channels.
void twr_uart_init(twr_uart_channel_t channel, twr_uart_baudrate_t baudrate, twr_uart_setting_t setting)
Initialize UART channel.
size_t twr_uart_async_write(twr_uart_channel_t channel, const void *buffer, size_t length)
Add data to be transmited in async mode.
void twr_uart_set_async_fifo(twr_uart_channel_t channel, twr_fifo_t *write_fifo, twr_fifo_t *read_fifo)
Set buffers for async transfers.
size_t twr_uart_write(twr_uart_channel_t channel, const void *buffer, size_t length)
Write data to UART channel (blocking call)
bool twr_uart_async_read_start(twr_uart_channel_t channel, twr_tick_t timeout)
Start async reading.
twr_uart_event_t
Callback events.
twr_uart_baudrate_t
UART baudrate.
void twr_uart_set_event_handler(twr_uart_channel_t channel, void(*event_handler)(twr_uart_channel_t, twr_uart_event_t, void *), void *event_param)
Set callback function.
bool twr_uart_async_read_cancel(twr_uart_channel_t channel)
Cancel async reading.
size_t twr_uart_async_read(twr_uart_channel_t channel, void *buffer, size_t length)
Get data that has been received in async mode.
size_t twr_uart_read(twr_uart_channel_t channel, void *buffer, size_t length, twr_tick_t timeout)
Read data from UART channel (blocking call)
void twr_uart_deinit(twr_uart_channel_t channel)
Deinitialize UART channel.
twr_uart_setting_t
UART setting.
@ TWR_UART_UART1
UART channel UART1.
@ TWR_UART_UART2
UART channel UART2.
@ TWR_UART_UART0
UART channel UART0.
@ TWR_UART_EVENT_ASYNC_READ_DATA
Event is reading done.
@ TWR_UART_EVENT_ASYNC_READ_TIMEOUT
Event is timeout.
@ TWR_UART_EVENT_ASYNC_WRITE_DONE
Event is writting done.
@ TWR_UART_BAUDRATE_38400
UART baudrat 38400 bps.
@ TWR_UART_BAUDRATE_921600
UART baudrat 921600 bps.
@ TWR_UART_BAUDRATE_57600
UART baudrat 57600 bps.
@ TWR_UART_BAUDRATE_115200
UART baudrat 115200 bps.
@ TWR_UART_BAUDRATE_19200
UART baudrat 19200 bps.
@ TWR_UART_BAUDRATE_9600
UART baudrat 9600 bps.
@ TWR_UART_SETTING_8N1_5
8N1_5: 8 data bits, none parity bit, 1.5 stop bits
@ TWR_UART_SETTING_8E2
8E2: 8 data bits, even parity bit, 2 stop bit
@ TWR_UART_SETTING_8O1
8O1: 8 data bits, odd parity bit, 1 stop bit
@ TWR_UART_SETTING_7O1
7O1: 7 data bits, odd parity bit, 1 stop bit
@ TWR_UART_SETTING_8O2
8O2: 8 data bits, odd parity bit, 2 stop bit
@ TWR_UART_SETTING_7N2
7N2: 7 data bits, none parity bit, 2 stop bits
@ TWR_UART_SETTING_8N1
8N1: 8 data bits, none parity bit, 1 stop bit
@ TWR_UART_SETTING_7N1
7N1: 7 data bits, none parity bit, 1 stop bit
@ TWR_UART_SETTING_8E1
8E1: 8 data bits, even parity bit, 1 stop bit
@ TWR_UART_SETTING_7E1_5
7E1_5: 7 data bits, even parity bit, 1.5 stop bit
@ TWR_UART_SETTING_8O1_5
8O1_5: 8 data bits, odd parity bit, 1.5 stop bit
@ TWR_UART_SETTING_8E1_5
8E1_5: 8 data bits, even parity bit, 1.5 stop bit
@ TWR_UART_SETTING_7N1_5
7N1_5: 7 data bits, none parity bit, 1.5 stop bits
@ TWR_UART_SETTING_7E2
7E2: 7 data bits, even parity bit, 2 stop bit
@ TWR_UART_SETTING_8N2
8N2: 8 data bits, none parity bit, 2 stop bits
@ TWR_UART_SETTING_7E1
7E1: 7 data bits, even parity bit, 1 stop bit
@ TWR_UART_SETTING_7O2
7O2: 7 data bits, odd parity bit, 2 stop bit
@ TWR_UART_SETTING_7O1_5
7O1_5: 7 data bits, odd parity bit, 1.5 stop bit
Structure of FIFO instance.