Firmware SDK
twr_i2c.c
1 #include <twr_i2c.h>
2 #include <twr_tick.h>
3 #include <stm32l0xx.h>
4 #include <twr_scheduler.h>
5 #include <twr_ds28e17.h>
6 #include <twr_module_sensor.h>
7 #include <twr_module_x1.h>
8 #include <twr_onewire.h>
9 #include <twr_system.h>
10 #include <twr_gpio.h>
11 
12 #define _TWR_I2C_TX_TIMEOUT_ADJUST_FACTOR 1.5
13 #define _TWR_I2C_RX_TIMEOUT_ADJUST_FACTOR 1.5
14 
15 #define _TWR_I2C_MEMORY_ADDRESS_SIZE_8BIT 1
16 #define _TWR_I2C_MEMORY_ADDRESS_SIZE_16BIT 2
17 #define _TWR_I2C_RELOAD_MODE I2C_CR2_RELOAD
18 #define _TWR_I2C_AUTOEND_MODE I2C_CR2_AUTOEND
19 #define _TWR_I2C_SOFTEND_MODE (0x00000000U)
20 #define _TWR_I2C_NO_STARTSTOP (0x00000000U)
21 #define _TWR_I2C_GENERATE_START_WRITE I2C_CR2_START
22 #define _TWR_I2C_BYTE_TRANSFER_TIME_US_100 80
23 #define _TWR_I2C_BYTE_TRANSFER_TIME_US_400 20
24 
25 #define __TWR_I2C_RESET_PERIPHERAL(__I2C__) {__I2C__->CR1 &= ~I2C_CR1_PE; __I2C__->CR1 |= I2C_CR1_PE; }
26 
27 static struct
28 {
29  int initialized_semaphore;
30  twr_i2c_speed_t speed;
31  I2C_TypeDef *i2c;
32 
33 } _twr_i2c[] = {
34  [TWR_I2C_I2C0] = { .initialized_semaphore = 0, .i2c = I2C2 },
35  [TWR_I2C_I2C1] = { .initialized_semaphore = 0, .i2c = I2C1 },
36  [TWR_I2C_I2C_1W]= { .initialized_semaphore = 0, .i2c = NULL }
37 };
38 
39 static twr_tick_t tick_timeout;
40 static twr_ds28e17_t ds28e17;
41 
42 static bool _twr_i2c_mem_write(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length, uint8_t *buffer, uint16_t length);
43 static bool _twr_i2c_mem_read(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length, uint8_t *buffer, uint16_t length);
44 static bool _twr_i2c_req_mem_write(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length);
45 static bool _twr_i2c_req_mem_read(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length);
46 static void _twr_i2c_config(I2C_TypeDef *i2c, uint8_t device_address, uint8_t length, uint32_t mode, uint32_t Request);
47 static bool _twr_i2c_watch_flag(I2C_TypeDef *i2c, uint32_t flag, FlagStatus status);
48 static bool _twr_i2c_is_ack_failure(I2C_TypeDef *i2c);
49 static bool _twr_i2c_read(I2C_TypeDef *i2c, const void *buffer, size_t length);
50 static bool _twr_i2c_write(I2C_TypeDef *i2c, const void *buffer, size_t length);
51 static uint32_t twr_i2c_get_timeout_ms(twr_i2c_channel_t channel, size_t length);
52 static uint32_t twr_i2c_get_timeout_us(twr_i2c_channel_t channel, size_t length);
53 static void _twr_i2c_timeout_begin(uint32_t timeout_ms);
54 static bool _twr_i2c_timeout_is_expired(void);
55 static void _twr_i2c_restore_bus(I2C_TypeDef *i2c);
56 
58 {
59  if (++_twr_i2c[channel].initialized_semaphore != 1)
60  {
61  return;
62  }
63 
64  if (channel == TWR_I2C_I2C0)
65  {
68 
71 
74 
75  GPIOB->OTYPER |= GPIO_OTYPER_OT_10 | GPIO_OTYPER_OT_11; // Set open-drain output
76  GPIOB->OSPEEDR |= GPIO_OSPEEDER_OSPEED10 | GPIO_OSPEEDER_OSPEED11;
77 
78  // Enable I2C2 peripheral clock
79  RCC->APB1ENR |= RCC_APB1ENR_I2C2EN;
80 
81  // Errata workaround
82  RCC->APB1ENR;
83 
84  // Enable I2C2 peripheral
85  I2C2->CR1 |= I2C_CR1_PE;
86 
87  twr_i2c_set_speed(channel, speed);
88  }
89  else if (channel == TWR_I2C_I2C1)
90  {
93 
96 
99 
100  GPIOB->OTYPER |= GPIO_OTYPER_OT_8 | GPIO_OTYPER_OT_9; // Set open-drain output
101  GPIOB->OSPEEDR |= GPIO_OSPEEDER_OSPEED8 | GPIO_OSPEEDER_OSPEED9;
102 
103  // Enable I2C1 peripheral clock
104  RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
105 
106  // Errata workaround
107  RCC->APB1ENR;
108 
109  // Enable I2C1 peripheral
110  I2C1->CR1 |= I2C_CR1_PE;
111 
112  twr_i2c_set_speed(channel, speed);
113  }
114  else if (channel == TWR_I2C_I2C_1W)
115  {
116  twr_onewire_t *onewire;
117 
118  #if TWR_USE_X1_FOR_I2C_1W != 1
121  onewire = twr_module_sensor_get_onewire();
122  #else
124  onewire = twr_module_x1_get_onewire();
125  #endif
126 
127  twr_tick_t t_timeout = twr_tick_get() + 500;
128 
129  while (twr_tick_get() < t_timeout)
130  {
131  continue;
132  }
133 
134  twr_ds28e17_init(&ds28e17, onewire, 0x00);
135 
136  twr_i2c_set_speed(channel, speed);
137  }
138 }
139 
141 {
142  if (--_twr_i2c[channel].initialized_semaphore != 0)
143  {
144  return;
145  }
146 
147  if (channel == TWR_I2C_I2C0)
148  {
149  // Disable I2C2 peripheral
150  I2C2->CR1 &= ~I2C_CR1_PE;
151 
152  // Disable I2C2 peripheral clock
153  RCC->APB1ENR &= ~RCC_APB1ENR_I2C2EN;
154 
155  // Errata workaround
156  RCC->APB1ENR;
157 
158  GPIOB->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEED10_Msk | GPIO_OSPEEDER_OSPEED11_Msk);
159 
162 
165  }
166  else if (channel == TWR_I2C_I2C1)
167  {
168  // Disable I2C1 peripheral
169  I2C1->CR1 &= ~I2C_CR1_PE;
170 
171  // Disable I2C1 peripheral clock
172  RCC->APB1ENR &= ~RCC_APB1ENR_I2C1EN;
173 
174  // Errata workaround
175  RCC->APB1ENR;
176 
177  GPIOB->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEED8_Msk | GPIO_OSPEEDER_OSPEED9_Msk);
178 
181 
184  }
185  else if (channel == TWR_I2C_I2C_1W)
186  {
187  twr_ds28e17_deinit(&ds28e17);
188 
191  // TODO: deinit twr_module_sensor and twr_ds28e17
192  }
193 }
194 
196 {
197  return _twr_i2c[channel].speed;
198 }
199 
201 {
202  uint32_t timingr;
203 
204  if (_twr_i2c[channel].initialized_semaphore == 0)
205  {
206  return;
207  }
208 
209  if (channel == TWR_I2C_I2C_1W)
210  {
211  twr_ds28e17_set_speed(&ds28e17, speed);
212 
213  _twr_i2c[channel].speed = speed;
214 
215  return;
216  }
217 
218  if (speed == TWR_I2C_SPEED_400_KHZ)
219  {
220  timingr = 0x301d1d;
221  }
222  else
223  {
224  timingr = 0x709595;
225  }
226 
227  if (channel == TWR_I2C_I2C0)
228  {
229  I2C2->CR1 &= ~I2C_CR1_PE;
230  I2C2->TIMINGR = timingr;
231  I2C2->CR1 |= I2C_CR1_PE;
232  }
233  else if (channel == TWR_I2C_I2C1)
234  {
235  I2C1->CR1 &= ~I2C_CR1_PE;
236  I2C1->TIMINGR = timingr;
237  I2C1->CR1 |= I2C_CR1_PE;
238  }
239 
240  _twr_i2c[channel].speed = speed;
241 }
242 
243 bool twr_i2c_write(twr_i2c_channel_t channel, const twr_i2c_transfer_t *transfer)
244 {
245  if (_twr_i2c[channel].initialized_semaphore == 0)
246  {
247  return false;
248  }
249 
250  if (channel == TWR_I2C_I2C_1W)
251  {
252  return twr_ds28e17_write(&ds28e17, transfer);
253  }
254 
255  I2C_TypeDef *i2c = _twr_i2c[channel].i2c;
256 
257  twr_system_pll_enable();
258 
259  // Get maximum allowed timeout in ms
260  uint32_t timeout_ms = _TWR_I2C_TX_TIMEOUT_ADJUST_FACTOR * twr_i2c_get_timeout_ms(channel, transfer->length);
261 
262  _twr_i2c_timeout_begin(timeout_ms);
263 
264  bool status = false;
265 
266  // Wait until bus is not busy
267  if (_twr_i2c_watch_flag(i2c, I2C_ISR_BUSY, SET))
268  {
269  // Configure I2C peripheral and try to get ACK on device address write
270  _twr_i2c_config(i2c, transfer->device_address << 1, transfer->length, I2C_CR2_AUTOEND, _TWR_I2C_GENERATE_START_WRITE);
271 
272  // Try to transmit buffer and update status
273  status = _twr_i2c_write(i2c, transfer->buffer, transfer->length);
274  }
275 
276  // If error occured ( timeout | NACK | ... ) ...
277  if (status == false)
278  {
279  // Reset I2C peripheral to generate STOP conditions immediately
280  __TWR_I2C_RESET_PERIPHERAL(i2c);
281  }
282 
283  twr_system_pll_disable();
284 
285  return status;
286 
287 }
288 
289 bool twr_i2c_read(twr_i2c_channel_t channel, const twr_i2c_transfer_t *transfer)
290 {
291  if (_twr_i2c[channel].initialized_semaphore == 0)
292  {
293  return false;
294  }
295 
296  if (channel == TWR_I2C_I2C_1W)
297  {
298  return twr_ds28e17_read(&ds28e17, transfer);
299  }
300 
301  I2C_TypeDef *i2c = _twr_i2c[channel].i2c;
302 
303  twr_system_pll_enable();
304 
305  // Get maximum allowed timeout in ms
306  uint32_t timeout_ms = _TWR_I2C_RX_TIMEOUT_ADJUST_FACTOR * twr_i2c_get_timeout_ms(channel, transfer->length);
307 
308  _twr_i2c_timeout_begin(timeout_ms);
309 
310  bool status = false;
311 
312  // Wait until bus is not busy
313  if (_twr_i2c_watch_flag(i2c, I2C_ISR_BUSY, SET))
314  {
315  // Configure I2C peripheral and try to get ACK on device address read
316  _twr_i2c_config(i2c, transfer->device_address << 1, transfer->length, I2C_CR2_AUTOEND, I2C_CR2_START | I2C_CR2_RD_WRN);
317 
318  // Try to receive data to buffer and update status
319  status = _twr_i2c_read(i2c, transfer->buffer, transfer->length);
320  }
321 
322  // If error occured ( timeout | NACK | ... ) ...
323  if (status == false)
324  {
325  _twr_i2c_restore_bus(i2c);
326  }
327 
328  twr_system_pll_disable();
329 
330  return status;
331 }
332 
334 {
335  if (_twr_i2c[channel].initialized_semaphore == 0)
336  {
337  return false;
338  }
339 
340  if (channel == TWR_I2C_I2C_1W)
341  {
342  return twr_ds28e17_memory_write(&ds28e17, transfer);
343  }
344 
345  I2C_TypeDef *i2c = _twr_i2c[channel].i2c;
346 
347  // Enable PLL and disable sleep
348  twr_system_pll_enable();
349 
350  uint16_t transfer_memory_address_length =
351  (transfer->memory_address & TWR_I2C_MEMORY_ADDRESS_16_BIT) != 0 ? _TWR_I2C_MEMORY_ADDRESS_SIZE_16BIT : _TWR_I2C_MEMORY_ADDRESS_SIZE_8BIT;
352 
353  // If memory write failed ...
354  if (!_twr_i2c_mem_write(i2c, transfer->device_address << 1, transfer->memory_address, transfer_memory_address_length, transfer->buffer, transfer->length))
355  {
356  // Reset I2C peripheral to generate STOP conditions immediately
357  __TWR_I2C_RESET_PERIPHERAL(i2c);
358 
359  // Disable PLL and enable sleep
360  twr_system_pll_disable();
361 
362  return false;
363  }
364 
365  // Disable PLL and enable sleep
366  twr_system_pll_disable();
367 
368  return true;
369 }
370 
372 {
373  if (_twr_i2c[channel].initialized_semaphore == 0)
374  {
375  return false;
376  }
377 
378  if (channel == TWR_I2C_I2C_1W)
379  {
380  return twr_ds28e17_memory_read(&ds28e17, transfer);
381  }
382 
383  I2C_TypeDef *i2c = _twr_i2c[channel].i2c;
384 
385  // Enable PLL and disable sleep
386  twr_system_pll_enable();
387 
388  uint16_t transfer_memory_address_length =
389  (transfer->memory_address & TWR_I2C_MEMORY_ADDRESS_16_BIT) != 0 ? _TWR_I2C_MEMORY_ADDRESS_SIZE_16BIT : _TWR_I2C_MEMORY_ADDRESS_SIZE_8BIT;
390 
391  // If error occurs during memory read ...
392  if (!_twr_i2c_mem_read(i2c, transfer->device_address << 1, transfer->memory_address, transfer_memory_address_length, transfer->buffer, transfer->length))
393  {
394  _twr_i2c_restore_bus(i2c);
395 
396  // Disable PLL and enable sleep
397  twr_system_pll_disable();
398 
399  return false;
400  }
401 
402  // Disable PLL and enable sleep
403  twr_system_pll_disable();
404 
405  return true;
406 }
407 
408 bool twr_i2c_memory_write_8b(twr_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint8_t data)
409 {
410  twr_i2c_memory_transfer_t transfer;
411 
412  transfer.device_address = device_address;
413  transfer.memory_address = memory_address;
414  transfer.buffer = &data;
415  transfer.length = 1;
416 
417  return twr_i2c_memory_write(channel, &transfer);
418 }
419 
420 bool twr_i2c_memory_write_16b(twr_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint16_t data)
421 {
422  uint8_t buffer[2];
423 
424  buffer[0] = data >> 8;
425  buffer[1] = data;
426 
427  twr_i2c_memory_transfer_t transfer;
428 
429  transfer.device_address = device_address;
430  transfer.memory_address = memory_address;
431  transfer.buffer = buffer;
432  transfer.length = 2;
433 
434  return twr_i2c_memory_write(channel, &transfer);
435 }
436 
437 bool twr_i2c_memory_read_8b(twr_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint8_t *data)
438 {
439  twr_i2c_memory_transfer_t transfer;
440 
441  transfer.device_address = device_address;
442  transfer.memory_address = memory_address;
443  transfer.buffer = data;
444  transfer.length = 1;
445 
446  return twr_i2c_memory_read(channel, &transfer);
447 }
448 
449 bool twr_i2c_memory_read_16b(twr_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint16_t *data)
450 {
451  uint8_t buffer[2];
452 
453  twr_i2c_memory_transfer_t transfer;
454 
455  transfer.device_address = device_address;
456  transfer.memory_address = memory_address;
457  transfer.buffer = buffer;
458  transfer.length = 2;
459 
460  if (!twr_i2c_memory_read(channel, &transfer))
461  {
462  return false;
463  }
464 
465  *data = buffer[0] << 8 | buffer[1];
466 
467  return true;
468 }
469 
470 static bool _twr_i2c_mem_write(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length, uint8_t *buffer, uint16_t length)
471 {
472  // Get maximum allowed timeout in ms
473  uint32_t timeout_ms = _TWR_I2C_TX_TIMEOUT_ADJUST_FACTOR * twr_i2c_get_timeout_ms(i2c == I2C2 ? TWR_I2C_I2C0 : TWR_I2C_I2C1, length);
474 
475  _twr_i2c_timeout_begin(timeout_ms);
476 
477  // Wait until bus is not busy
478  if (!_twr_i2c_watch_flag(i2c, I2C_ISR_BUSY, SET))
479  {
480  return false;
481  }
482 
483  // Send slave address and memory address
484  if (!_twr_i2c_req_mem_write(i2c, device_address, memory_address, memory_address_length))
485  {
486  return false;
487  }
488 
489  // Set size of data to write
490  _twr_i2c_config(i2c, device_address, length, _TWR_I2C_AUTOEND_MODE, _TWR_I2C_NO_STARTSTOP);
491 
492  // Perform I2C transfer
493  return _twr_i2c_write(i2c, buffer, length);
494 }
495 
496 static bool _twr_i2c_mem_read(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length, uint8_t *buffer, uint16_t length)
497 {
498  // Get maximum allowed timeout in ms
499  uint32_t timeout_ms = _TWR_I2C_RX_TIMEOUT_ADJUST_FACTOR * twr_i2c_get_timeout_ms(i2c == I2C2 ? TWR_I2C_I2C0 : TWR_I2C_I2C1, length);
500 
501  _twr_i2c_timeout_begin(timeout_ms);
502 
503  // Wait until bus is not busy
504  if (!_twr_i2c_watch_flag(i2c, I2C_ISR_BUSY, SET))
505  {
506  return false;
507  }
508 
509  // Send slave address and memory address
510  if (!_twr_i2c_req_mem_read(i2c, device_address, memory_address, memory_address_length))
511  {
512  return false;
513  }
514 
515  // Set size of data to read
516  _twr_i2c_config(i2c, device_address, length, I2C_CR2_AUTOEND, I2C_CR2_START | I2C_CR2_RD_WRN);
517 
518  // Perform I2C transfer
519  return _twr_i2c_read(i2c, buffer, length);
520 }
521 
522 static bool _twr_i2c_req_mem_write(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length)
523 {
524  _twr_i2c_config(i2c, device_address, memory_address_length, _TWR_I2C_RELOAD_MODE, _TWR_I2C_GENERATE_START_WRITE);
525 
526  // Wait until TXIS flag is set
527  if (!_twr_i2c_watch_flag(i2c, I2C_ISR_TXIS, RESET))
528  {
529  return false;
530  }
531 
532  // If memory address size is 16Bit
533  if (memory_address_length == _TWR_I2C_MEMORY_ADDRESS_SIZE_16BIT)
534  {
535  // Send MSB of memory address
536  i2c->TXDR = (memory_address >> 8) & 0xff;
537 
538  // Wait until TXIS flag is set
539  if (!_twr_i2c_watch_flag(i2c, I2C_ISR_TXIS, RESET))
540  {
541  return false;
542  }
543  }
544 
545  // Send LSB of memory address
546  i2c->TXDR = memory_address & 0xff;
547 
548  // Wait until TCR flag is set
549  if (!_twr_i2c_watch_flag(i2c, I2C_ISR_TCR, RESET))
550  {
551  return false;
552  }
553 
554  return true;
555 }
556 
557 static bool _twr_i2c_req_mem_read(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length)
558 {
559  _twr_i2c_config(i2c, device_address, memory_address_length, _TWR_I2C_SOFTEND_MODE, _TWR_I2C_GENERATE_START_WRITE);
560 
561  // Wait until TXIS flag is set
562  if (!_twr_i2c_watch_flag(i2c, I2C_ISR_TXIS, RESET))
563  {
564  return false;
565  }
566 
567  // If memory address size is 16Bit
568  if (memory_address_length == _TWR_I2C_MEMORY_ADDRESS_SIZE_16BIT)
569  {
570  // Send MSB of memory address
571  i2c->TXDR = (memory_address >> 8) & 0xff;
572 
573  // Wait until TXIS flag is set
574  if (!_twr_i2c_watch_flag(i2c, I2C_ISR_TXIS, RESET))
575  {
576  return false;
577  }
578  }
579 
580  // Send LSB of memory address
581  i2c->TXDR = memory_address & 0xff;
582 
583  // Wait until TC flag is set
584  if (!_twr_i2c_watch_flag(i2c, I2C_ISR_TC, RESET))
585  {
586  return false;
587  }
588 
589  return true;
590 }
591 
592 static void _twr_i2c_config(I2C_TypeDef *i2c, uint8_t device_address, uint8_t length, uint32_t mode, uint32_t Request)
593 {
594  uint32_t reg;
595 
596  // Get the CR2 register value
597  reg = i2c->CR2;
598 
599  // clear tmpreg specific bits
600  reg &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP);
601 
602  // update tmpreg
603  reg |= (device_address & I2C_CR2_SADD) | (length << I2C_CR2_NBYTES_Pos) | mode | Request;
604 
605  // update CR2 register
606  i2c->CR2 = reg;
607 }
608 
609 static bool _twr_i2c_watch_flag(I2C_TypeDef *i2c, uint32_t flag, FlagStatus status)
610 {
611  while ((i2c->ISR & flag) == status)
612  {
613  if ((flag == I2C_ISR_STOPF) || (flag == I2C_ISR_TXIS))
614  {
615  // Check if a NACK is not detected ...
616  if (!_twr_i2c_is_ack_failure(i2c))
617  {
618  return false;
619  }
620  }
621 
622  if (_twr_i2c_timeout_is_expired())
623  {
624  return false;
625  }
626  }
627  return true;
628 }
629 
630 static bool _twr_i2c_is_ack_failure(I2C_TypeDef *i2c)
631 {
632  if ((i2c->ISR & I2C_ISR_NACKF) != 0)
633  {
634  // Wait until STOP flag is reset
635  // AutoEnd should be initialized after AF
636  while ((i2c->ISR & I2C_ISR_STOPF) == 0)
637  {
638  if (_twr_i2c_timeout_is_expired())
639  {
640  return false;
641  }
642  }
643 
644  // Clear NACKF flag
645  i2c->ICR = I2C_ISR_NACKF;
646 
647  // Clear STOP flag
648  i2c->ICR = I2C_ISR_STOPF;
649 
650  // If a pending TXIS flag is set ...
651  if ((i2c->ISR & I2C_ISR_TXIS) != 0)
652  {
653  // ... write a dummy data in TXDR to clear it
654  i2c->TXDR = 0;
655  }
656 
657  // Flush TX register if not empty
658  if ((i2c->ISR & I2C_ISR_TXE) == 0)
659  {
660  i2c->ISR |= I2C_ISR_TXE;
661  }
662 
663  // Clear Configuration Register 2
664  i2c->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN);
665 
666  return false;
667  }
668 
669  return true;
670 }
671 
672 static bool _twr_i2c_read(I2C_TypeDef *i2c, const void *buffer, size_t length)
673 {
674  uint8_t *p = (uint8_t *) buffer;
675 
676  while (length > 0)
677  {
678  // Wait until RXNE flag is set
679  if (!_twr_i2c_watch_flag(i2c, I2C_ISR_RXNE, RESET))
680  {
681  return false;
682  }
683 
684  // Read data from RXDR
685  *p++ = i2c->RXDR;
686 
687  length--;
688  }
689 
690  // No need to Check TC flag, with AUTOEND mode the stop is automatically generated
691 
692  // Wait until STOPF flag is reset
693  if (!_twr_i2c_watch_flag(i2c, I2C_ISR_STOPF, RESET))
694  {
695  return false;
696  }
697 
698  // Clear STOP flag
699  i2c->ICR = I2C_ICR_STOPCF;
700 
701  // Clear Configuration Register 2
702  i2c->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN);
703 
704  return true;
705 }
706 
707 static uint32_t twr_i2c_get_timeout_ms(twr_i2c_channel_t channel, size_t length)
708 {
709  uint32_t timeout_us = twr_i2c_get_timeout_us(channel, length);
710 
711  return (timeout_us / 1000) + 10;
712 }
713 
714 static uint32_t twr_i2c_get_timeout_us(twr_i2c_channel_t channel, size_t length)
715 {
717  {
718  return _TWR_I2C_BYTE_TRANSFER_TIME_US_100 * (length + 3);
719  }
720  else
721  {
722  return _TWR_I2C_BYTE_TRANSFER_TIME_US_400 * (length + 3);
723  }
724 }
725 
726 static bool _twr_i2c_write(I2C_TypeDef *i2c, const void *buffer, size_t length)
727 {
728  uint8_t *p = (uint8_t *) buffer;
729 
730  while (length > 0)
731  {
732  // Wait until TXIS flag is set
733  if (!_twr_i2c_watch_flag(i2c, I2C_ISR_TXIS, RESET))
734  {
735  return false;
736  }
737 
738  // Write data to TXDR
739  i2c->TXDR = *p++;
740 
741  length--;
742  }
743 
744  // No need to Check TC flag, with AUTOEND mode the stop is automatically generated
745 
746  // Wait until STOPF flag is reset
747  if (!_twr_i2c_watch_flag(i2c, I2C_ISR_STOPF, RESET))
748  {
749  return false;
750  }
751 
752  // Clear STOP flag
753  i2c->ICR = I2C_ICR_STOPCF;
754 
755  // Clear Configuration Register 2
756  i2c->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN);
757 
758  return true;
759 }
760 
761 void _twr_i2c_timeout_begin(uint32_t timeout_ms)
762 {
763  tick_timeout = twr_tick_get() + timeout_ms;
764 }
765 
766 bool _twr_i2c_timeout_is_expired(void)
767 {
768  bool is_expired = tick_timeout < twr_tick_get() ? true : false;
769 
770  return is_expired;
771 }
772 
773 static void _twr_i2c_restore_bus(I2C_TypeDef *i2c)
774 {
775  // TODO Take care of maximum rate on clk pin
776 
777  if (i2c == I2C2)
778  {
779  GPIOB->MODER &= ~GPIO_MODER_MODE10_Msk;
780  GPIOB->MODER |= GPIO_MODER_MODE10_0;
781  GPIOB->BSRR = GPIO_BSRR_BS_10;
782 
783  GPIOB->MODER &= ~GPIO_MODER_MODE11_Msk;
784 
785  while (!(GPIOB->IDR & GPIO_IDR_ID11))
786  {
787  GPIOB->ODR ^= GPIO_ODR_OD10;
788  }
789 
790  GPIOB->BSRR = GPIO_BSRR_BR_11;
791  GPIOB->BSRR = GPIO_BSRR_BS_11;
792 
793  // Configure I2C peripheral to transmit softend mode
794  _twr_i2c_config(i2c, 0xfe, 1, I2C_CR2_STOP, _TWR_I2C_SOFTEND_MODE);
795 
796  // Reset I2C peripheral to generate STOP conditions immediately
797  __TWR_I2C_RESET_PERIPHERAL(i2c);
798 
799  GPIOB->MODER &= ~GPIO_MODER_MODE10_Msk;
800  GPIOB->MODER |= GPIO_MODER_MODE10_1;
801 
802  GPIOB->MODER &= ~GPIO_MODER_MODE11_Msk;
803  GPIOB->MODER |= GPIO_MODER_MODE11_1;
804 
805  GPIOB->BSRR = GPIO_BSRR_BR_10;
806  GPIOB->BSRR = GPIO_BSRR_BR_11;
807  }
808  else
809  {
810  GPIOB->MODER &= ~GPIO_MODER_MODE8_Msk;
811  GPIOB->MODER |= GPIO_MODER_MODE8_0;
812  GPIOB->BSRR = GPIO_BSRR_BS_8;
813 
814  GPIOB->MODER &= ~GPIO_MODER_MODE9_Msk;
815 
816  while (!(GPIOB->IDR & GPIO_IDR_ID9))
817  {
818  GPIOB->ODR ^= GPIO_ODR_OD9;
819  }
820 
821  GPIOB->BSRR = GPIO_BSRR_BR_9;
822  GPIOB->BSRR = GPIO_BSRR_BS_9;
823 
824  // Configure I2C peripheral to transmit softend mode
825  _twr_i2c_config(i2c, 0xfe, 1, I2C_CR2_STOP, _TWR_I2C_SOFTEND_MODE);
826 
827  // Reset I2C peripheral to generate STOP conditions immediately
828  __TWR_I2C_RESET_PERIPHERAL(i2c);
829 
830  GPIOB->MODER &= ~GPIO_MODER_MODE8_Msk;
831  GPIOB->MODER |= GPIO_MODER_MODE8_1;
832 
833  GPIOB->MODER &= ~GPIO_MODER_MODE9_Msk;
834  GPIOB->MODER |= GPIO_MODER_MODE9_1;
835 
836  GPIOB->BSRR = GPIO_BSRR_BR_8;
837  GPIOB->BSRR = GPIO_BSRR_BR_11;
838  }
839 }
I2C channel 1wire.
Definition: twr_i2c.h:24
bool twr_i2c_write(twr_i2c_channel_t channel, const twr_i2c_transfer_t *transfer)
Write to I2C channel.
Definition: twr_i2c.c:243
void twr_gpio_set_mode(twr_gpio_channel_t channel, twr_gpio_mode_t mode)
Set mode of operation for GPIO channel.
Definition: twr_gpio.c:367
GPIO channel operates in alternate mode AF6.
Definition: twr_gpio.h:138
twr_onewire_t * twr_module_x1_get_onewire(void)
Initialize and get Instance 1-Wire for channel B.
Definition: twr_module_x1.c:50
bool twr_i2c_memory_write(twr_i2c_channel_t channel, const twr_i2c_memory_transfer_t *transfer)
Memory write to I2C channel.
Definition: twr_i2c.c:333
uint32_t memory_address
8-bit I2C memory address (it can be extended to 16-bit format if OR-ed with TWR_I2C_MEMORY_ADDRESS_16...
Definition: twr_i2c.h:63
bool twr_i2c_memory_write_16b(twr_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint16_t data)
Memory write 2 bytes to I2C channel.
Definition: twr_i2c.c:420
I2C communication speed is 100 kHz.
Definition: twr_i2c.h:33
GPIO channel P17, SDA1.
Definition: twr_gpio.h:66
uint8_t device_address
7-bit I2C device address
Definition: twr_i2c.h:45
bool twr_module_sensor_init(void)
Initialize Sensor Module.
void twr_gpio_set_pull(twr_gpio_channel_t channel, twr_gpio_pull_t pull)
Set pull-up/pull-down configuration for GPIO channel.
Definition: twr_gpio.c:340
GPIO channel operates in analog mode.
Definition: twr_gpio.h:114
bool twr_ds28e17_set_speed(twr_ds28e17_t *self, twr_i2c_speed_t speed)
Set I2C speed.
Definition: twr_ds28e17.c:35
I2C transfer parameters.
Definition: twr_i2c.h:42
bool twr_ds28e17_memory_write(twr_ds28e17_t *self, const twr_i2c_memory_transfer_t *transfer)
Memory write to I2C.
Definition: twr_ds28e17.c:82
twr_i2c_speed_t twr_i2c_get_speed(twr_i2c_channel_t channel)
Get speed I2C channel.
Definition: twr_i2c.c:195
GPIO channel SCL0.
Definition: twr_gpio.h:78
GPIO channel has no pull-up/pull-down.
Definition: twr_gpio.h:90
GPIO channel SDA0.
Definition: twr_gpio.h:81
bool twr_i2c_memory_read(twr_i2c_channel_t channel, const twr_i2c_memory_transfer_t *transfer)
Memory read from I2C channel.
Definition: twr_i2c.c:371
void twr_i2c_set_speed(twr_i2c_channel_t channel, twr_i2c_speed_t speed)
Set I2C channel speed.
Definition: twr_i2c.c:200
GPIO channel has pull-up.
Definition: twr_gpio.h:93
void * buffer
Pointer to buffer which is being written or read.
Definition: twr_i2c.h:66
bool twr_module_sensor_set_pull(twr_module_sensor_channel_t channel, twr_module_sensor_pull_t pull)
Set pull of Sensor Module channel.
GPIO channel P16, SCL1.
Definition: twr_gpio.h:63
void twr_gpio_init(twr_gpio_channel_t channel)
Initialize GPIO channel.
Definition: twr_gpio.c:325
GPIO channel operates in alternate mode AF4.
Definition: twr_gpio.h:132
void twr_i2c_init(twr_i2c_channel_t channel, twr_i2c_speed_t speed)
Initialize I2C channel.
Definition: twr_i2c.c:57
twr_i2c_speed_t
I2C communication speed.
Definition: twr_i2c.h:30
bool twr_module_sensor_onewire_power_up(void)
Semaphore for 1Wire Power up: for R1.1 set VDD On, for R1.0 pull up 56R on channel A...
struct twr_onewire_t twr_onewire_t
1-Wire instance
Definition: twr_onewire.h:14
I2C memory transfer parameters.
Definition: twr_i2c.h:57
bool twr_i2c_memory_read_16b(twr_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint16_t *data)
Memory read 2 bytes from I2C channel.
Definition: twr_i2c.c:449
uint64_t twr_tick_t
Timestamp data type.
Definition: twr_tick.h:16
bool twr_i2c_memory_write_8b(twr_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint8_t data)
Memory write 1 byte to I2C channel.
Definition: twr_i2c.c:408
twr_tick_t twr_tick_get(void)
Get absolute timestamp since start of program.
Definition: twr_tick.c:7
Channel has no pull.
size_t length
Length of buffer which is being written or read.
Definition: twr_i2c.h:51
twr_i2c_channel_t
I2C channels.
Definition: twr_i2c.h:15
bool twr_ds28e17_memory_read(twr_ds28e17_t *self, const twr_i2c_memory_transfer_t *transfer)
Memory read from I2C.
Definition: twr_ds28e17.c:107
I2C channel I2C1.
Definition: twr_i2c.h:21
bool twr_i2c_read(twr_i2c_channel_t channel, const twr_i2c_transfer_t *transfer)
Read from I2C channel.
Definition: twr_i2c.c:289
void * buffer
Pointer to buffer which is being written or read.
Definition: twr_i2c.h:48
I2C channel I2C0.
Definition: twr_i2c.h:18
bool twr_ds28e17_write(twr_ds28e17_t *self, const twr_i2c_transfer_t *transfer)
Write to I2C.
Definition: twr_ds28e17.c:60
size_t length
Length of buffer which is being written or read.
Definition: twr_i2c.h:69
#define TWR_I2C_MEMORY_ADDRESS_16_BIT
This flag extends I2C memory transfer address from 8-bit to 16-bit.
Definition: twr_i2c.h:11
bool twr_i2c_memory_read_8b(twr_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint8_t *data)
Memory read 1 byte from I2C channel.
Definition: twr_i2c.c:437
bool twr_ds28e17_read(twr_ds28e17_t *self, const twr_i2c_transfer_t *transfer)
Read from I2C.
Definition: twr_ds28e17.c:71
void twr_ds28e17_init(twr_ds28e17_t *self, twr_onewire_t *onewire, uint64_t device_number)
Initialize DS28E17.
Definition: twr_ds28e17.c:14
bool twr_module_x1_init(void)
Initialize X1 Module.
Definition: twr_module_x1.c:19
void twr_ds28e17_deinit(twr_ds28e17_t *self)
Deinitialize DS28E17.
Definition: twr_ds28e17.c:25
twr_onewire_t * twr_module_sensor_get_onewire(void)
Initialize and get Instance 1-Wire for channel B.
void twr_i2c_deinit(twr_i2c_channel_t channel)
Deitialize I2C channel.
Definition: twr_i2c.c:140
I2C communication speed is 400 kHz.
Definition: twr_i2c.h:36
uint8_t device_address
7-bit I2C device address
Definition: twr_i2c.h:60
DS28E17 instance.
Definition: twr_ds28e17.h:13